Semiconductor processing has moved towards the production of smaller and smaller devices having greater computing capability. The reduction in the size of electronic devices and the increase in density of transistors in a given unit area results in increased power required and dissipated. Enhanced semiconductor fabrication techniques, such as silicon-on-insulator (SOI) processing, increase metal wiring requirements because of the increase transistor density and power decoupling requirements.
Specific applications, such as arrays, are impacted by the amount of wiring needed to fully enable the application. Wiring in semiconductor devices is generally configured in multiple planes, especially when multiple devices are configured in a dense pattern. Metal wiring in a given plane of the device reduces the area available in that plane for other electronic functions and severely constrains device performance. These problems undermine the overall objective to fabricate smaller, more densely packed devices having superior performance.
Prior publications which are exemplary of SOI process technology include Chatterjee, U.S. Pat. Nos. 4,889,832 and 4,982,266. Chatterjee discloses an integrated circuit structure in which metal layers both above and below an active circuit are interconnected. Chatterjee proposes an improved method of forming such an integrated circuit structure by utilizing an etch stop layer formed on a silicon surface.
Kato et al., U.S. Pat. No. 4,939,568 teaches a stacked semiconductor integrated circuit structure and method of forming the same, in which conducting posts extend between device surfaces. This is intended to allow large scale integrated circuit manufacturing.
Pfiester, U.S. Pat. No. 4,966,864 discloses a semiconductor device and method in which a silicon substrate is formed with a doped region, with the doped region being connected to an electrode by a conducting bridge. This invention is intended to overcome pitting or etching problems encountered in previous fabrication techniques.
McCarthy, U.S. Pat. No. 5,488,012, discloses SOI wafers and improved methods for forming buried regions therein. The invention is particularly useful in silicon-on-glass substrates.
Iwamatsu, U.S. Pat. No. 5,294,821, discloses SOI technology which is intended to provide more uniform electrical characteristics including a reduction in breakdown voltage. Iwamatsu proposes a device having active layers diffused into the substrate to stabilize the electrical characteristics of the device.
Tyson et al., U.S. Pat. No. 5,145,802, discloses a SOI circuit which includes a set of buried body ties that provide a local ohmic contact to the transistor bodies disposed on an insulating layer. This is intended to provide a path for holes generated by impact ionization and also act as a potential shield between the substrate and the transistor sources.
Kang et al., U.S. Pat. No. 5,286,670, teaches a method of manufacturing a semiconductor device having buried elements with electrical characteristics. Kang uses a complex system of buried electrical elements in the substrate, bonding the substrate to the silicon that is to become the SOI region. One exemplary use for the buried elements is as capacitors in memory cells. But, in fact, Kang et al. add to the complexity of device fabrication without resolving concerns of wiring density.
Conventional SOI technology reduces a large portion of the drain capacitance and, to a lesser extent, the gate capacitance because the insulator layer does not have many available free carriers. In operation, however, carriers flow through the transistor and resistive heating occurs in the gate. Undesirable floating body effects including transistor hysteresis and threshold shifts may occur if the transistor body is allowed to electrically float. The electrical bias placed on the device by the remaining carriers causes a narrowing in the depth of the transistor body channel which affects performance.
Decoupling capacitance, moreover, is significantly reduced on traditional semiconductor-on-insulator structures. The structure experiences a phenomena referred to as power-supply collapse so that the voltage swing level between a logical one and a logical zero is reduced, e.g., a logical zero may no longer be at ground voltage.
Semiconductor on insulator devices are very desirable given the desirable electrical isolation obtained from the SOI structure. However, this structure creates undesirable thermal insulation which, in turn, causes troublesome joule heating in the devices. An alternative embodiment of the invention provides a low-resistance thermal path from the transistor diffusion to a plane in the bulk substrate, providing a thermal sink which reduces thermal effects.